library ieee;
use ieee.std_logic_1164.all;

entity aludec_tb is
end aludec_tb;

architecture behav of aludec_tb is
    component aludec
        port(
        AluOp: in std_logic_vector(1 downto 0);
        Funct: in std_logic_vector(5 downto 0);
        AluControl: out std_logic_vector(2 downto 0)
        );
    end component;

    signal AO_s: std_logic_vector(1 downto 0);
    signal Fun_s: std_logic_vector(5 downto 0);
    signal AC_s: std_logic_vector(2 downto 0);

begin
    AD0: aludec port map(AO_s, Fun_s, AC_s);

    process
    type input_array is array (natural range <>) of std_logic_vector(7 downto 0);
    type output_array is array (natural range <>) of std_logic_vector(2 downto 0);
    constant inPatterns: input_array := ("00XXXXXX", "01XXXXXX", "1X100000",
                                        "1X100010", "1X100100", "1X100101",
                                        "1X101010");
    constant outPatterns: output_array := ("010", "110", "010","110", "000",
                                        "001", "111");
    begin
        for i in inPatterns'range loop
            AO_s <= inPatterns(i)(7 downto 6);
            Fun_s <= inPatterns(i)(5 downto 0);
            wait for 1 ns;
            assert AC_s = outPatterns(i);
        end loop;
        wait;
    end process;
end behav;
